My most interesting failures, #1: Anagram architecture

Back in 1993 I came up with a paper design for a multicore CPU architecture that was strikingly similar to SUN's Niagra architecture, which came out over a decade later. My design probably shared some aspects with multicores that shipped before Niagra did, too.

I wrote about it publicly, only once, but by the time I stopped working on it, a year later, in Dec, 1993, it was well developed enough to file a few patents, had I chosen to do so, but I didn't. Someone that "knew" that the crossbar switches inherent in the design were impossible to build, convinced me I was barking up the wrong tree. (That person worked for SUN, amusingly enough)

It used an ISA roughly derived from the MIPS architecture and a stack based register set much like the transputer T800. Probably the most innovative feature from my perspective was that I used RAMBUS chips hooked up serially, rather than in parallel, and divided the memory up into as many 8 bit paths as I had pins available. Getting the RAM industry to produce sticks of ram in this segmented fashion would have been nearly impossible! Soldiering the chips directly on the buses was my answer but this put a hard outer limit on the amount of memory you could have with RAMBUS....

Still, I figured that the narrow memory buses would be a way of producing a series of CPU chips of various performance levels. I thought, also, that you could eventually produce smarter ram sticks - with cache and a MMU on board each one - if you did things this way.

The design also could do DMA at the virtual memory level, rather than at the physical addressing level. Memcpy was basically an op-code that suspended that CPU and handed off the operation to the MMU. This took best advantage of the slow memory buses because it could do burst transfers - so common in the message passing operating systems in academia at the time.

I called it the Anagram Architecture because, being stack based, and highly threaded, you could rewind and restart various sorts of instruction in a super-scalar fashion, and run more jumbled up processes in parallel, more simply than you could with a classic Van Neuman architecture.

I don't know when the crossbar switches I envisioned became buildable, but they are everywhere now. I've dabbled with hardware design ever since, and played with a few FPGAs, but ideas like 32 bit and 64 bit memory busses are firmly embedded in everything, and developing a competitive CPU from scratch a pointless, expensive, exercise. Not that that stops people. Two interesting CPUs I've seen recently are the Propeller and David May, creator of the Transputer, is working on Xmos.

Labels: failures, patents

  ¶ 5:32 PM